Some integrated circuits (i.e., chips) require supply voltages of different levels, which may be generated "on-chip" using voltage generators incorporated into the chip. For on-chip generated supply voltages that are higher than the externally supplied voltage or voltages, charge pumps are typically used as the voltage generator. FIG. 1 is a block diagram illustrative of a conventional integrated circuit charge pump 10 used to generate a supply voltage V.sub.H having a level that is higher than the level of the externally provided supply voltage. Charge pump 10 includes a main pump stage (WPS) 11, a well pump stage (WPS) 13, and two P-channel transistor P14 and P15 serving as pass gates. MPS 11 and WPS 13 are each connected to a VDD supply bus and a ground bus to receive power from an external power source (not shown) providing supply voltage VDD. In addition, MPS 11 and WPS 13 are connected to receive "n" (n representing an integer greater than zero) pump control signals through a control line 16. The output leads of MPS 11 and WPS 13 are connected to the sources of P-channel transistors P14 and 15, respectively.
P-channel transistors P14 and P15 have their gates connected to a line 18 to receive a pump boost control signal PMPBST. When asserted (i.e., a logic low level in this embodiment), signal PMPBST has a boosted level (i.e., a level that is higher than the normal VDD level) and is used to control charge transfer from the output leads of MPS 11 and WPS 13.
The drain of P-channel transistor P14 is connected to output lead 19, whereas the drain of P-channel transistor P15 is connected to the well of P-channel transistor P14. In this example, P-channel transistor P14 is implemented in an N-well. As is well known in the art of semiconductor devices, the well must be maintained at a potential (i.e., V.sub.WELL) that is equal to or greater than the highest potential at either the source or the drain of P-channel transistor P14 for proper transistor operation. However, due to fluctuations in load current, the level of voltage V.sub.H at output lead 19 (i.e. the drain of P-channel transistor P14) will at times be greater than the level of the voltage at output lead of MPS 11 (i.e., the source of P-channel transistor P14). In addition, the voltage level at the source of transistor P14 at times is greater than the level of voltage V.sub.H. Thus, simply tying the well to the source or the drain of P-channel transistor P14 would not be effective.
To address this issue, charge pump 10 uses WPS 13 to maintain the level of voltage V.sub.WELL at a predetermined level that is higher than the maximum voltage levels of the source and drain of P-channel transistor 14. Those skilled in the art will appreciate that the capacitance and leakage of the well of P-channel transistor P15 is typically relatively small and, thus, the voltage level at the source of P-channel transistor P15 will generally always be greater or equal to the voltage level of the well. Consequently, tying the drain of P-channel transistor P15 to the well is effective in maintaining the voltage level of the well at or above the voltage levels at the source and drains of P-channel transistor P15.
To maintain supply voltage V.sub.H at the desired level, a control circuit (not shown) conventionally provides the pump control signals on line 16 so as to cause MPS 11 and WPS 13 to transfer charge to the sources of P-channel transistors P14 and P15, respectively. Pump boost signal PMPBST is used to control the state of P-channel transistors P14 and P15 to transfer charge from MPS 11 and WPS 13 to output lead 19 and to the well of P-channel transistor 14, respectively. More specifically, P-channel transistors P14 and P15 are turned off when MPS 11 and WPS 13 are charging their pumping capacitors, which are connected to the sources of P-channel transistors P14 and P15, respectively. In particular, MPS 11 and WPS 13 boost the voltage at their respective output leads to a level significantly greater than the level of the external supply voltage. This boosting is typically achieved by charging a capacitor in the pump stage so that a first lead is at the ground potential while the second lead is at the external supply voltage level. Then the pump stage increases the voltage level at the first lead, thereby boosting, at least initially, the voltage at the second lead to a level higher than the external supply voltage level.
As MPS 11 and WPS 13 have boosted the voltage level at the sources of P-channel transistors P14 and P15, signal PMPBST is provided so as to turn on P-channel transistors P14 and P15, thereby allowing charge to redistribute from the pumping capacitors of MPS 11 and WPS 13, to the sources of P-channel transistors P14 and P15, and to output lead 19 and the well of P-channel transistor P14, respectively. In this way, charge pump 10 generates supply voltage V.sub.H and maintains the level of voltage V.sub.WELL so as to be equal to or higher than the levels of the voltages at the source and drain of P-channel transistor P14.
However, if the voltage level at the well of P-channel transistor P14 gets too high, the risk of junction breakdown in devices connected to the well is increased. This problem can be exacerbated during burn-in testing during which the external supply voltage is increased to a level that is higher than the normal operational level. Accordingly, there is a need for a charge pump that can limit the voltage at nodes internal to the charge pump.